In both embedded and non-embedded CPUs, there are predominant Instruction Set Architectures (ISAs) for which large bodies of software exist that could be “accelerated” for performance, or “translated” to a myriad of capable processors that could present better cost/performance benefits, provided that they could transparently access the relevant software. One also finds dominant CPU architectures that are locked in time to their ISA, and cannot evolve in performance or market reach. Such CPUs would benefit from a software-oriented processor co-architecture.
Program code conversion methods and apparatus to facilitate such acceleration, translation and co-architecture capabilities are disclosed, for example, in published PCT application WO00/22521, and others.